Programming and Compiling for Intel® Many Integrated Core Architecture

Compiler Methodology for Intel® MIC Architecture

This methodology enables you to determine your application's suitability for performance gains using Intel® Many Integrated Core Architecture (Intel® MIC Architecture).

Complete each of the following tasks in the order shown below.

• Preparing for the Intel® Many Integrated Core Architecture
  • Application Analysis for Intel® MIC Architecture Suitability
  • Expectations for User Source Code Changes
    • Cache Blocking Techniques
    • Memory Layout Transformations
    • Large Page Considerations ^Updated!
    • Element-wise Alignment Requirements for Data Accesses
• New User Compiler Basic Usage
• Compiler Essentials with accompanying QUICKLAB EXERCISES:
• Compiler pragmas/directives
• Efficient Parallelization
  • OpenMP* - Getting started using OpenMP with the Intel compilers
    • Best Known Methods for Using OpenMP on Intel(R) Many Integrated Core (Intel(R) MIC) Architecture
    • Thread Affinity Control with the Intel OpenMP Runtime ^Updated!
    • OpenMP Loop Scheduling
    • OpenMP Related Tips
  • Parallelization Using Intel® MPI
    
  • Parallelization with Intel® Cilk™ Plus
  • Parallelization using Intel® Threading Building Blocks (Intel® TBB)
• Vectorization Essentials
  • Vectorization for C or C++ Users with Intel® Cilk™ Plus Array Notations and Elemental Functions
  • Guided Autoparallelism (GAP)
  • Fortran Array Data and Arguments and Vectorization ^Updated!
  • Vectorization and Optimization Reports
  • Overview of vec-report and new -vec-report6 option
  • How to correlate vec-report line-numbers with source line numbers.
  • Data Alignment to Assist Vectorization ^Updated!
  • Pointer Aliasing and Vectorization
  • Outer Loop Vectorization ^Updated!
  • Outer Loop Vectorization via Intel® Cilk™ Plus Array Notations (for C/C++ Users)
  • Tradeoffs between array-notation long-vector and short-vector coding (for C/C++ Users)
  • Utilizing Full Vectors and Use of Option -opt-assume-safe-padding
  • Vectorization of Loops Using Random Number Functions
  • Avoid Manual Loop Unrolling
  • Other common Vectorization Techniques
• Advanced Optimizations
  
  • The Floating Point Model  - balancing performance with accuracy and reproducibility
  • Floating Point Differences - between Xeon and MIC
  • Low Precision Optimizations
  • Prefetching on Intel® MIC Architecture ^Updated!
  • Scheduling for Multiple Threads on Intel® MIC Architecture ^Updated!
  • Intel® MIC Architecture Streaming Stores ^Updated!
  • Selective Use of gatherhint/scatterhint Instructions
  • Data first-touch considerations and optimizations
  • Data Movement and Initialization: Optimization and Control
• Native and Offload Programming Models
  • Building Native Applications for Intel® MIC Architecture
  • The Heterogeneous Offload Programming Model
  • Effective Use of Compiler Features for Offloading ^Updated!
  • Asynchronous Offload whitepaper (C++ and Fortran)
  • Asynchronous Offload Presentations (C++, Fortran)
  • Cross-Compilation Challenges
  • How to Achieve Peak Transfer Rate (C++, Fortran)
  • Techniques to Reduce Offload-related Memory Allocation Overheads (C++, Fortran)
  • Taking Advantage of Offload Pointer Association and alloc/into Keywords (C++,Fortran)